1. Field of the Invention
The prevent invention relates to a relief technique of a faulty block containing a faulty memory cell which does not operate normally in a semiconductor memory device, in particular, a redundancy relief technique in a nonvolatile semiconductor memory device.
2. Description of the Related Art
In a recent semiconductor memory device, since yields of memory cells tend to be decreased with increase and complexity in manufacturing processes due to miniaturization and large capacity, to improve the yields of the semiconductor memory device itself, various relief techniques with respect to a memory cell array containing a faulty memory cell which does not operate normally have been proposed. Such relief techniques include a redundancy relief technique in which a redundant block to replace a faulty block containing a faulty memory cell is prepared in a semiconductor memory device in advance and, when the faulty block is detected in total inspection (screening) for failure selection before shipment, the faulty block is replaced with the redundant block.
Here, the above-mentioned redundancy relief technique will be described. FIG. 3 shows a configuration of an NOR-type flash memory cell array in which memory cells 112 formed at intersections between word lines 102 and bit lines 106 are arranged in a matrix form. This memory cell array is configured by a plurality of memory blocks 113 consisting of the plurality of memory cells 112 formed at the intersections between the predetermined number of word lines 102 and the predetermined number of bit lines 106 and replacement with a redundancy block is performed in units of blocks. Specifically, for example, when a faulty memory cell is detected in screening, a faulty block containing the faulty memory cell is identified and a faulty address identifying the faulty block is stored in a faulty memory cell address storage part. In a normal operation, an input address input from the outside of the semiconductor memory device (device) is compared with the faulty address and, when both addresses matches each other, the replaceable redundant block is selected and the selection of the faulty block is prohibited. In this manner, so-called redundancy relief function is realized.
Next, writing and erasure of data to and from a flash memory will be described with reference to FIG. 4. The flash memory writes data thereto by making a threshold voltage of the memory cell higher than a predetermined value through a writing operation and erases data therefrom by making the threshold voltage of the memory cell lower than a predetermined value through an erasing operation. This realizes the storage of data.
More specifically, the writing operation of data to the flash memory is performed by applying 0 V to a source 100, a positive voltage V1 of 5 V, for example, to a drain 101 and a positive voltage V2 of 9 V, for example, to the word line 102. Thus, hot electrons generated by passing a current between the source 100 and the drain 101 are injected into a floating gate 103. As a result, the threshold voltage of the memory cell becomes higher.
Subsequently, the erasing operation of the flash memory will be described in detail with reference to FIG. 5. FIG. 5 is a flowchart showing an example of the erasing operation. First, as an erasure preprocess, a process for preventing excessive erasure of the memory cells is performed on all memory cells in a selected block (step S1). Specifically, a positive voltage V3 of 6 V, for example, which is lower than the positive voltage V2 is applied to the word lines 102 to weakly perform writing in advance.
Subsequently, data is erased from all memory cells in the selected block to lower the threshold voltage of the memory cells (step S2). Specifically, the erasure of data from the flash memory is performed by applying a negative voltage V4 of −8 V, for example, to the word lines 102 and a positive voltage V5 of 8 V, for example, to a P-type region 104. Thus, electrons in the floating gate 103 moves to the P-type region 104 and the threshold voltage of the memory cells becomes lower. Generally, since the P-type region 104 is commonly owned in the above-mentioned units of blocks, data is collectively erased from all memory cells in the memory block.
Subsequently, a comparison circuit such as a sense amplifier converts the threshold voltage of the memory cells into a current and compares the converted current with a reference current in magnitude (step S3). Here, when the threshold voltage of the memory cells is lower than a predetermined reference voltage, it is determined as Pass and in the other case, it is determined as Fail. Then, until it is determined as Pass in erasure verification in step S3, erasure in step S2 is repeated. If it is determined as Fail in step S3, the number of Fail determinations (the number of erasures in step S2) is calculated and it is determined whether or not the number of erasures is equal to or smaller than a prescribed number (step S4). When the number of erasures exceeds the prescribed number for any reason, it is determined as abnormal erasure, that is, inerasable. Furthermore, an abnormal completion signal indicating that the erasing operation has not normally completed is output to the outside of the device and the erasing operation is finished. If it is determined as Pass in step S3, as an erasure postprocess, a positive voltage V6 of 3 V, for example, which is lower than the positive voltage V2 is applied to the word lines 102, thereby weakly writing to excessively erased memory cells (step S5) and the erasing operation is finished.
Here, for example, in generally known flash memories, in particular, NOR-type flash memories, progressive failure cannot be completely detected in conventional screening, for example, in a shipment test including repeated accessing operations to the memory cell array such as the erasing operations and the writing operations.
The progressive failure will be described in detail with reference to FIG. 4. Since a PN junction diode is formed between the P-type region 104 and the N-type drain 101 in the flash memory shown in FIG. 4, a forward voltage is applied at the erasing operation. Furthermore, by applying a positive voltage lower than the high voltage V5 applied to the P-type region 104 by about 0.8 V, for example, to a contact region 105, a high electric field generates a strong electric field stress between the word line 102 and the contact 105. Therefore, an insulating film between the word line 102 and the contact 105, manufactured to be thin through miniaturization, could be deteriorated during the repeated erasing operations. Depending on the deterioration state of the insulating film, a short or current leakage occurs between the word line 102 and the contact 105 and thus a desired voltage cannot be applied to the word line 102 and the P-type region 104 at the erasing operation. As a result, there may cause a problem that time for the erasing operation of the memory cells is extended or erasure cannot be carried out. Furthermore, since the erasing operation is performed in units of blocks, when failure occurs in any memory cell in the memory block, the whole memory blocks containing the faulty memory cell are regarded as a faulty block.
Conventionally, to detect the progressive failure more satisfactorily, an accelerated test is carried out at the screening and E/W (erasure/writing) is repeatedly performed.
The accelerated test for the progressive failure will be described with reference to FIG. 6. As shown in FIG. 6, the NOR-type flash memory is configured so that a plurality of memory cells are connected to a bit line 106 in parallel. The accelerated test for the progressive failure is carried out as follows. A negative voltage V7 further lower than the negative voltage V4 is applied to the word line of each memory cell and a positive voltage V8 further higher than positive voltage V5 is applied to the P-type region 104, thereby applying larger electric field stress than that at the normal erasing operation between the word line 102 and the contact 105. Thus, the occurrence of the progressive failure is physically accelerated.
However, when the negative voltage V7 is too low or the positive voltage V8 is too high, in some cases, there is a possibility that the memory cell falls into the excessive erasure state. In addition, since the erasing operation is performed in units of blocks, there is a possibility that a plurality of memory cells on the same bit line 106 (a memory cell A107, a memory cell B108, a memory cell C109, etc.) fall into the excessive erasure state. For example, when weak writing to the memory cell A107 on the bit line 106 in the erasure postprocess, since the memory cells other than memory cell A107 are brought into an unselected state, 0 V is applied to the word line 110, the line 111, etc. At this time, the threshold voltage of the memory cell in the excessive erasure state is a low value such as 0.5 V. For this reason, in the state where a large number of memory cells in the excessive erasure state exist on the bit line 106, overall leakage current becomes large and the voltage at the bit lines 106 is lowered. Furthermore, since a potential difference between the source 100 and the drain 101 becomes small, a current passing between the source 100 and the drain 101 is reduced, resulting in that the hot electrons required for the writing to the memory cell A107 are reduced or do not occur. Therefore, since there is a possibility that the writing to the memory cells may not be performed when the negative voltage V7 is too low or the positive voltage V8 is too high, an electric field stress to be applied is limited. In consideration of these circumstances, disadvantageously it is difficult to carry out the accelerated test for the progressive failure in a short time.
Moreover, when E/W is repeatedly performed at the screening, it takes a long time to perform the E/W in the flash memory and thus the time for screening becomes longer.
Furthermore, even when the above-mentioned screening before shipment of the device is carried out, it is difficult to completely eliminate the progressive failure. Thus, failure may occur due to repeated E/W in normal operations after shipment of the device.
On the contrary, as a technique relating to measures against the progressive failure, for example, JP-A 03-116497 (1991) discloses a semiconductor memory device having a self-test circuit for testing all memory cells in a memory cell array and detecting a faulty memory cell region containing a faulty memory cell, in which in the case where there is an available redundant memory region, when a faulty memory region detected by the self-test circuit is selected, the redundant memory region is selected. Even after shipment of the device, this semiconductor memory device can replace the faulty memory region with the redundant memory region at the power-on or at the input of a control signal.
However, since the semiconductor memory device described in JP-A 03-116497 (1991) has the configuration of testing all memory cells in the memory cell array, when it is applied to the flash memory with long E/W time, it disadvantageously takes a long time to carry out the self-test. In recent years, the capacity of the flash memory tends to be increased and with the increase in the capacity, the time for the self-test has also increased remarkably. Specifically, when all memory cells are diagnosed as normal/faulty each at the power-on or at the input of the control signal and the faulty memory cell is replaced with the redundant memory cell on all such occasions, the time required until the device becomes available, for example, the device can execute a first data reading operation, becomes longer. Moreover, since the faulty memory cell is detected in the self-test at the power-on or at the input of the control signal, when progressive failure occurs during the erasing operation, disadvantageously, redundancy relief cannot apply to the faulty memory cell with progressive failure.